Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for forming a hole pattern in a semiconductor device.
As the integration of a semiconductor device drives decreases in size of features, the size of a hole pattern is decreasing as well. As the sizes of a semiconductor device further decrease, it is required to develop a patterning technology that overcomes the limitations in the analysis capability of current exposure equipment.
Meanwhile, highly integrated semiconductor devices also reduce the line width, which is also referred to as critical dimension, of storage nodes. However, current mask patterning technology cannot be used for patterning of a next-generation semiconductor device. To overcome the limitation, a patterning method of alternately performing a spacer patterning technology (SPT) process twice has been suggested.
However, the patterning method of alternately performing an SPT process twice has too many factors involving in the control of line width and uniformity, and its patterning performance is poor due to selectivity between stacks. Also, when double patterning technology (DPT) is used to perform a patterning process, line width of a desired dimension is hardly acquired due to limitation in analysis capacity of line patterning.
Therefore, it is required to develop a method that can overcome the limitation of a mask and form a micro hole pattern.